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C2N

Centre for Nanoscience and Nanotechnology
1 Projects, page 1 of 1
  • Funder: CHIST-ERA Project Code: CHIST-ERA-18-ACAI-005
    Partners: Université de Sherbrooke, IM2NP, C2N, IBM Research Zurich Laboratory

    Edge computing (EC) and the development of portable devices such as cell phones, autonomous robot or health tracking systems represent one of the big challenges for artificial intelligence (AI) deployment. These hardware systems present very tight constraints in terms of energy consumption and computing power that today’s AI strategies cannot cope with. While high power GPU are well adapted to deep neural network implementations that should strongly benefit to AI development, ultra-low power and robust computing with limited resources need to be proposed for EC applications. To this end, we propose to explore the hardware implementation of small-scale neural networks with limited complexity that could satisfy EC requirements. Notably, spiking neural networks present a real opportunity to this end since, they can combine low power operation and non-trivial computing functions as biological neural networks do. In fact, spiking neural networks (SNNs) of moderate size can reproduce important aspects that are not considered in state-of-the-art machine learning approaches: i) non-linear dynamical regime (i.e. synchronized, critic, driven by attractor dynamics, sequences of spikes) that might explain basic mechanisms in perception and ii) the fast computing that occurs in the brain even if neurons are slow. The UNICO project proposes to address the material implementation of such SNNs by integrating in a dedicated hardware, the key ingredients at work in such SNNs. In fact, we can anticipate that the physical implementation of such highly parallel systems will encounter strong limitations with conventional technologies. A real breakthrough for Information and Communication Technologies would be to capitalize on emerging nanotechnologies to implement efficiently these SNNs on an ultra-low power hardware. Here, state of the art analog resistive memory technologies, or memristive devices, will be developed and integrated in the Back End Of Line of CMOS for implementing analog SNNs. By gathering competences from material sciences, device engineering, neuromorphic engineering and machine learning, we will explore how such SNNs can be deployed on various computing tasks of interest for EC applications. The expected innovations at both the hardware and computing levels could benefit to a wide range of AI applications in the future.