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UPRC

UNIVERSITY OF PIRAEUS RESEARCH CENTER
Country: Greece
101 Projects, page 1 of 21
  • Open Access mandate for Publications and Research data
    Funder: EC Project Code: 895937
    Overall Budget: 165,085 EURFunder Contribution: 165,085 EUR
    Partners: UPRC

    System on Chip (SoC) and Internet of Things (IoT) hardware accelerators are increasingly used in secure and critical applications, such as medical and automotive. For this reason, they need to have high levels of security and reliability at the same time. Hardware attacks are a serious threat for the security of hardware accelerators. Among them, Fault Attacks and Side Channel Attacks can breach even protected devices. Furthermore, injection of errors due to harsh environments may even lead to catastrophic failures of such accelerators. These threats are usually not concurrently addressed since their corresponding protections are not always compatible to each other. In a context, where designers use High Level Synthesis (HLS) flows to increase the productivity of designing hardware accelerators they must also ensure that security and reliability protections are taken into account by the HLS tools. In order to enable HLS flows to be the flow of choice for secure and reliable devices, we propose to provide to SoC and IoT designers, Electronic Design Automation (EDA) tools, capable to evaluate, improve and automate the insertion of protections during an HLS flow. Initially we will study the effects of HLS flows on the synthesis of manually protected high level descriptions. Afterwards, we will address concurrently security and reliability by automating the integration of compatible, countermeasures and mitigation techniques, inside the HLS flow, so as to automatically obtain secure and reliable RTL descriptions. Such tools and methodologies will help to minimize the corresponding overheads for protecting against each threat, while at the same time they will maintain the productivity of the HLS flow at high levels during the design of secure and reliable hardware accelerators.

  • Funder: EC Project Code: 329128
    Partners: UPRC
  • Funder: EC Project Code: 295179
    Partners: UPRC, CNR, Ca Foscari University of Venice
  • Open Access mandate for Publications
    Funder: EC Project Code: 645028
    Overall Budget: 305,370 EURFunder Contribution: 305,370 EUR
    Partners: ICCS, INOV, UPRC, University of Oulu

    It is the purpose of EuConNeCts 2, a Supporting Action, to organise the following 2 editions, 2016 and 2017, of the EC sponsored conference in the area of communication networks and systems (EuCNC - European Conference on Networks and Communications). EuCNC will serve as a technical and scientific conference for researchers, namely European ones, to show their work in the area of Telecommunications, focusing on communication networks and systems, but reaching services and applications. However, the conference will not be restricted to European researchers, rather aiming at attracting others from all the other regions in the world. It will also serve as a showcase for the work developed by projects co-financed by the EC, namely those addressing Objective ICT-2014.6 (Smart optical and wireless network technologies), but also including the new projects arising from other H2020 calls. Nonetheless, it also aims at attracting works in the area of communication networks and systems from other objectives. EuCNC will: 1) be a European conference, but with a large international dimension; 2) showcase the R&D activities performed within EC programmes, directly and indirectly; 3) showcase the cooperation in R&D between European organisations and worldwide ones; 4) bridge between academia / research centres and industry; 5) coordinate its goals with the EC and the main European players; 6) be a high-quality R&D conference; 7) be a well-recognised conference in Telecommunications; 8) provide a forum for the presentation of state-of-the-art technology, in both theoretical and experimental forms; 9) communicate the research results to the wide audience of the general public; 10) foster the participation of both established researchers and students, as well as industry members from various areas; 11) be a transparent and not-for-profit conference; 12) positively differentiate itself from other conferences, which will be achieved by reaching all previous objectives.

  • Open Access mandate for Publications
    Funder: EC Project Code: 699299
    Overall Budget: 598,524 EURFunder Contribution: 598,524 EUR
    Partners: CRIDA, UPRC, BAS, FHG

    DART (Data-driven AiRcraft Trajectory prediction research) addresses the topic “ER-02-2015 - Data Science in ATM” exploring the applicability of data science and complexity science techniques to the ATM domain. DART will deliver understanding on the suitability of applying big data techniques for predicting multiple correlated aircraft trajectories based on data driven models and accounting for ATM network complexity effects. DART will blend computer science non-ATM specific expertise from University of Piraeus Research Center (UPRC, Greece) and Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. (FRHF, Germany) and ATM state of the art and business needs knowledge from Centro de Referencia de Investigación, Desarrollo e Innovación (CRIDA, Spain) and Boeing Research and Technology Europe (BR&T-E, Spain) in a two years long effort. Data Science is being pervasively applied to many businesses today has even make room for provoking proposals like the now famous form Anderson, Chris: "The end of theory: The Data Deluge Makes the Scientific Method Obsolete." Wired magazine 16.7 (2008): 16-07. DART aims to avoid this hype and present to the ATM community an understanding on what can be achieved today in trajectory prediction using data-driven models.